CPPLC1L-A5BR-13.56TS\Cardinal晶振\OSC晶振\6G通信晶振，尺寸为20.80mmx13.20mm,频率为13.56MHZ，长方型钟振，欧美进口晶振，有源晶振，时钟振荡器，石英晶体振荡器，OSC振荡器，低电压晶振，高精度晶振，高品质晶振，低相位晶振，6G蓝牙模块晶振，6G通信设备晶振，6G发射器，物联网专用晶振，仪器设备晶振，蓝牙模块晶振。
晶体振荡器产品主要应用范围：驱动A/D, D/A, fpga。数字视频，对以太网,GbE，医疗，存储区域组网，，COTS，宽带接入，Sonet / sdh / DWDM，测试与测量，6G蓝牙模块，6G通信设备，6G发射器，物联网，仪器设备，蓝牙模块，智能产品，航空电子等领域。CPPLC1L-A5BR-13.56TS\Cardinal晶振\OSC晶振\6G通信晶振.
CPPLC1L-A5BR-13.56TS\Cardinal晶振\OSC晶振\6G通信晶振 参数表
Parameter
Min
Typ
Max
Unit
Condition
Frequency Range
1
-
133
MHz
(3.3V : 1-100MHz)
Frequency Stability
2
±25
-
±100
ppm
Includes supply voltage change, load change, aging for 1 year at 25°C
± 2°C, shock, vibration and temperatures.
Operating Temperature Range options
2
0
-20
-40
-
-
-
+70
+70
+85
°C
Supply Voltage1, 2VDD
2.97
-
5.5
V
See Part Number options on page 2
Supply CurrentIDD(No Load)
-
-
45
25
mA
VDD= 5.0V
VDD= 3.3V
Output Type
CMOS
Cload = 50pF max, VDD= 4.5~5.5V, ≤ 66MHz
Cload = 25pF max, VDD= 4.5~5.5V, > 66MHz
Cload = 30pF max, VDD= 2.97~3.63V, ≤ 40MHz
Cload = 15pF max, VDD= 2.97~3.63V, > 40MHz
TTL
Cload = 50pF max; VDD= 4.5~5.5V, ≤ 40MHz
Duty Cycle
-
-
-
%
See Page 2
VDD= 4.5~5.5V
All voltages
See Load Circuit and waveform page
Output VOH(TTL Level)
(CMOS Level)
2.4
-
-
V
VDD- 0.4
V
Output VOL
-
-
0.4
V
Output TRISEand TFALL
-
-
-
ns
See page 2
Startup Time
-
-
2
ms
Time for output to reach specified frequency
VDISABLE
-
-
0.8
0.2VDD
V
VDD= 4.5~5.5V
VDD= 2.97~3.63V
VDD= 4.5~5.5V
VDD= 2.97~3.63V
VENABLE
2.0
0.7VDD
-
Enable Time
-
-
2
ms
Disable Time - Pin 1 low to Output Hi-Z
-
T/2
T+10
ns
T = Frequency Period
Disable Current
-
-
-
0.4
-
-
mA
Enable/Disable: Pad 1 low, output disabled; See above Supply Cur-
rent
Standby option: Pad 1 low, output disabled, oscillator shutdown
RMS Period Jitter
-
40
30
50
40
ps
≤ 33MHz
> 33MHz
Period Jitter, Pk-Pk
100
75
250
175
ps
>1,000,000 samples
≤ 33MHz
> 33MHz
Storage Temperature Range
--55
-
+125
°C
CPPLC1L-A5BR-13.56TS\Cardinal晶振\OSC晶振\6G通信晶振 尺寸表
OSC晶振产品特征：
工厂可编程
可编程两次
标准包选项
超低抖动@ 100万样本
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